Plenary Talks

Keynote 1

Prof. Hao-Chiao Hong (Electrical and Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan)
Title: Design of BIST Delta-Sigma ADC

Abstract: Automotive IC is an emerging segment of the IC industry whose CGAR doubles the average of the overall IC design. The main challenge of the automotive IC design is to maintain 100% reliability in harsh environment for over 15-year lifetime. Built-in self-test (BIST) techniques that enable continuously testing the IC thereby become essential for every circuit. However, BIST techniques for mixed-signal circuits are not as mature as the digital counterparts because of the lack of an adequate analog fault model, the difficulty of realizing linear analog stimulus sources on chip, and the circuit under test being highly sensitive to its loads. This talk takes the Delta-Sigma ADC, popular in sensor interfaces and other high-resolution applications, as an example to demonstrate how to realize a BIST mixed-signal circuit. First, I will introduce the transfer-function based analog fault model that covers both easy-to-test catastrophic faults and hard-to-test parametric faults. Then, the very first fully-integrated BIST Delta-Sigma ADC in the world will be illustrated. This BIST design not only achieve a high fault coverage and yield with a negligible silicon cost, but also a high test accuracy. Finally, I will introduce the other BIST Delta-Sigma ADC design that further improves the test accuracy without compromise of the silicon cost and yield.

Biography: Dr. Hao-Chiao Hong received his B.S., M.S., and Ph.D. degrees in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan in 1990, 1992, and 2003, respectively. From 1997 to 2001, he was with Taiwan Semiconductor Manufacturing Company (TSMC) where he developed mixed-signal IPs for customers and process vehicles. He joined Intellectual Property Library Company, HsinChu, Taiwan, as the senior manager of the analog IP department in Aug. 2001. He has been with National Chiao Tung University (NCTU), Hsinchu, Taiwan, R. O. C. since Feb. 2004 where he is currently a full professor of the Electrical and Computer Engineering Department.
His main research interests include the design-for-testability, built-in self-test, and calibration techniques for mixed-signal circuits, as well as high performance mixed-signal and sensor IC design. Dr. Hong received the best paper awards from the IEEE CASI in 2017, the tenth VTTW in 2016, and the VLSI-DAT in 2009. He also received the best advisor award in the IC design competition of the Macronix Golden Silicon Award in 2012.

Keynote 2

Dr. Koji Asami (Advantest Corp.)
Title: Signal Processing Techniques for Testing RF, Mixed-signal and Analog ICs

Abstract: Testing an Integrated Circuit (IC) examines whether the IC is correctly manufactured as designed. When testing an analog IC, such as RF and Mixed-signal, among others, it is necessary to measure its performance, and in the past various kinds of dedicated, electronic measurement instruments were used for specialized measurements. Since around the 2nd half of 1970s, DSP-based testing has become mainstream, which can perform various measurements with the identical measurement system by using analog-to-digital converters and digital-to-analog converters in combination with digital signal processing. Using this method, in addition to basic performance analysis, such as spectrum analysis, more complicated analyses have been able to perform. In this talk, signal processing techniques for testing analog ICs from basic to application will be introduced.

Biography: Koji Asami received the master's degree in electronic engineering and Ph.D. degree in electronics and information engineering from Gunma University, Japan, in 1991 and 2009 respectively. He has worked with Advantest Corporation at their Gunma R&D Center since 1991, where he dedicated his time to researching signal processing techniques for mixed-signal and RF LSI test, including the digital modulation analysis. He has also been a visiting professor at graduate school of science and technology in Gunma University since 2015. His research interests include signal processing algorithm for testing RF and Analog devices and improving the Automatic Test Equipment (ATE) performance. He serves as a member of the technical program committee of the IEEE International Test Conference in Asia, 2019. He is a member of IEEE, IEICE and IEEJ.

Keynote 3

Mr. Atsushi Motozawa (Renesas Electronics)
Title: Phase-Locked Loop Circuit Design — From Basics to State-of-The-Art and Industrial Practices —

Abstract: Phase-locked loops (PLLs) are utilized in many SoCs to generate many different output clocks from one input clock. PLLs in LSIs multiply the input clock and provide the output clocks for MPUs, MCUs, data converters, and so on. In many SoCs, the frequency range of the output clocks is from a few hundreds MHz to a couple of GHz. Several PLLs are used in one IC to generate different frequencies, reduce clock skew due to clock distribution, recover a clock from a data signal, etc. So small PLLs are required to reduce costs and make products more competitive. This talk presents PLL fundamentals including their applications, building blocks, and principles. Tips to design PLLs will also be included in my talk. Then, I will introduce dual-path PLL architecture that can make smaller PLLs compared to common architecture with the same transfer functions. In addition to these topics, I will introduce hybrid PLL architecture that can achieve a small circuit and low jitter at the same time.

Biography: Atsushi Motozawa received B.S. and M.S. degrees in electrical engineering from Gunma University, Gunma, Japan, in 2006 and 2008, respectively. He joined Renesas Technology Corp., Takasaki, Japan, in 2008, where he was engaged in development of an RX analog front end for NFC LSIs. From 2010 to 2014, he was with Renesas Electronics Corp., Kawasaki, Japan, where he was engaged in designing sensors and a low power BGR for industrial ICs, and PLLs for automotive ICs. From 2014, he was with Renesas System Design, Co., Ltd. Since 2017, he has been with Renesas Electronics Corp., Kodaira, Japan. He is engaged in designing PLLs for SoCs.

Presentation Data (PDF: 1.05MB)

Last Update: Aug. 29, 2019