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| Publication (発表論文) |
< Journal Paper (原著論文) >
[1] Kiichi Niitsu, Shinmo Kang, Vishal V. Kulkarni, Hiroki Ishikuro, and Tadahiro Kuroda,
"A 14 GHz AC-Coupled Clock Distribution Scheme with Phase Averaging
Technique Using Sigle LC-VCO and Distributed Phase Interpolators,"
accepted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki
Ishikuro, and Tadahiro Kuroda, "Analysis and Techniques for Mitigating
Interference from Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling
Link for Low-Power 3D System Integration," accepted to IEEE Transactions
on Very Large Scale Integration (VLSI) Systems.
[3] Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada,
Naohiko Irie, Hiroki Ishikuro, and Tadahiro Kuroda, "Modeling and
Experimental Verification of Misalignment Tolerance in Inductive-Coupling
Inter-Chip Link for Low-Power 3D System Integration," IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 8, pp. 1238-1243,
Aug. 2010.
[4]Makoto Saen, Kenichi Osada, Yasuyuki Ookuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga,
Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, and
Tadahiro Kuroda, "3-D System Integration of Processor and Multi-Stacked
SRAMs Using Inductive-Coupling Link," IEEE Journal of Solid-State
Circuits, Vol. 45, No. 4, pp. 856-862, Jun. 2010.
[5] Kiichi Niitsu, Yuan Yuxiang, Hiroki Ishikuro, and Tadahiro Kuroda, "A 33% Improvement
in Efficiency of Wireless Inter-Chip Power Delivery by Thin Film Magnetic
Material for Three-Dimensional System Integration," Japanese Journal
of Applied Physics, Vol. 48, 04C073 (5 pages), Apr., 2009.
[6] Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro and Tadahiro Kuroda, "A 750 Mb/s, 12 pJ/b, 6-to-10
GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna," IEEE Journal
of Solid-State Circuits, Vol. 44, No. 2, pp. 394-403, Feb. 2009.
[7] Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, and Tadahiro Kuroda, "A 0.14pJ/bit Inductive-Coupling
Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE
Journal of Solid-State Circuits, Vol. 43, No. 1, pp. 285-291, Jan., 2008.
[8] Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, and Tadahiro Kuroda, "Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link,” IEICE Transactions on Electronics, Vol.E90-C, No. 4, pp. 829-835, Apr., 2007.
[9] Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki
Mizuno, Hiroki Ishikuro, and Tadahiro Kuroda, "60% Power Reduction
in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique,"
Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2215-2219, Apr.,
2007.
[10] Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai,
and Tadahiro Kuroda, "A 1Tb/s 3W Inductive-Coupling Transceiver for
3D-Stacked Inter-Chip Clock and Data Link," IEEE Journal of Solid-State
Circuits, Vol. 42, No. 1, pp. 111-122, Jan., 2007.
< International Conference Papers (国際会議発表論文) >
[1] Satoshi Uemori, Takahiro J. Yamaguchi, Satoshi Ito, Yohei Tan, Haruo
Kobayashi, Nobukazu Takai, Kiichi Niitsu, and Nobuyoshi Ishikawa, "ADC Linearity Test Signal Generation Algorithm," accepted to IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010), Dec. 2010.
[2] Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori,
Nobukazu Takai, Kiichi Niitsu, Takahiro J. Yamaguchi, Tatsuji Matsuura, and Nobuyoshi Ishikawa, "SAR
ADC That is Configurable to Optimize Yield," accepted to IEEE Asia
Pacific Conference on Circuits and Systems (APCCAS 2010), Dec. 2010.
[3] Satoshi Ito, Shigeyuki Nishimura, Haruo Kobayashi, Satoshi Uemori,
Yohei Tan, Nobukazu Takai, Takahiro J. Yamaguchi, and Kiichi Niitsu, "Stochastic TDC Architecture with Self-Calibration," accepted
to IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010),
Dec. 2010.
[4] Keita Takatsu, Kiichi Niitsu, Tsunaaki Shidei, Noriyuki Miura, and Tadahiro Kuroda, "A 0.45V-to-2.7V
Inductive-Coupling Level Shifter," accepted to IEEE Asian Solid-State
Circuits Conference (A-SSCC 2010), Nov. 2010.
[5] Kiichi Niitsu, Vishal V. Kurkarni, Kang Shinmo, Hiroki Ishikuro, and Tadahiro Kuroda, "A 14GHz AC-Coupled Clock Distribution Using Single LC-VCO and Distributed Phase Interpolators," International Conference on Solid State Devices and Materials (SSDM 2009), Extended Abstracts, pp. 82-83, Oct., 2009.
[6] Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa,
Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, and Hideharu Amano, "MuCCRA-Cube:
a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link,"
IEEE International Conference on Field Programmable Logic and Applications
(FPL 2009), Proceedings, pp. 1-6, Sep., 2009.
[7] Kenichi Osada, Makoto Saen, Yasuyuki Ookuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga,
Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, and
Tadahiro Kuroda, "3D System Integration of Processor and Multi- Stacked
SRAMs by Using Inductive-Coupling Links," IEEE Symposium on VLSI Circuits
(SoVC 2009), Digest of Technical Papers, pp. 256-257, Jun., 2009.
[8] Yoshinori Kohama, Yasufumi Sugimori, Shotaro Saito, Yohei Hasegawa,
Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Hideharu Amano, and Tadahiro Kuroda, "A Scalable 3D Processor by Homogeneous Chip Stacking with Inductive-Coupling Link," IEEE Symposium on VLSI Circuits (SoVC 2009), Digest of Technical Papers, pp. 94-95, Jun., 2009.
[9] Kiichi Niitsu, Yuan Yuxiang, Hiroki Ishikuro, and Tadahiro Kuroda, "High Efficiency
Inductive-Coupling Power Delivery With Sandwiching Thin Films of Magnetic
Material," IEEE International Magnetics Conference (INTERMAG 2009),
Digest of Technical Papers, pp. 59, May, 2009.
[10] Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga,
Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko
Irie, Toshihiro Hattori, Atsushi Hasegawa, and Tadahiro Kuroda, "An
Inductive-Coupling Link for 3D Integration of a 90nm CMOS Processor and
a 65nm CMOS SRAM," IEEE International Solid-State Circuits Conference
(ISSCC 2009), Digest of Technical Papers, pp.480-481, Feb., 2009.
[11] Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, and Tadahiro Kuroda, "A 65fJ/b Inductive-Coupling Inter-Chip Transceiver Using Charge Recycling Technique for Power-Aware 3D System Integration," IEEE Asian Solid-State Circuits Conference (A-SSCC 2008), Proceedings of Technical Papers, pp.97-100, Nov., 2008.
[12] Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kenichi Osada, Naohiko Irie, Hiroki
Ishikuro, and Tadahiro Kuroda, "Misalignment Tolerance in Inductive-Coupling
Inter-Chip Link for 3D System Integration," International Conference
on Solid State Devices and Materials (SSDM 2008), Extended Abstracts, pp.86-87,
Sep., 2008.
[13] Kiichi Niitsu, Yuan Yuxiang, Hiroki Ishikuro, and Tadahiro Kuroda, "A 33% Improvement
in Efficiency of Wireless Inter-Chip Power Delivery Using Thin Film Magnetic
Material," International Conference on Solid State Devices and Materials
(SSDM 2008), Extended Abstracts, pp.492-493, Sep., 2008.
[14] Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, and Tadahiro Kuroda, "Interference from Power/Signal Lines and to SRAM Circuits in 65nm CMOS Inductive-Coupling Link," IEEE Asian Solid-State Circuits Conference (A-SSCC 2007), Proceedings of Technical Papers, pp.131-134, Nov., 2007.
[15] Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Muneo
Fukaishi, Hiroki Ishikuro, and Tadahiro Kuroda, "60% Power Reduction
in Inductive-Coupling Inter-Chip Link by Current-Sensing Technique,"
International Conference on Solid State Devices and Materials (SSDM 2006),
Extended Abstracts, pp.64-65, Sep., 2006.
[16] Mari Inoue, Noriyuki Miura, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai,
and Tadahiro Kuroda, “Daisy Chain for Power Reduction in Inductive-Coupling
CMOS Link,” IEEE Symposium on VLSI Circuits (SoVC 2006), Digest of Technical
Papers, pp.80-81, Jun., 2006.
[17] Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, and Tadahiro Kuroda, “A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link,” International Solid-State Circuits Conference (ISSCC 2006), Digest of Technical Papers, pp.424-425, Feb., 2006.
< Book Chapter (著書) >
[1] Kiichi Niitsu and Tadahiro Kuroda, "An Inductive-Coupling Inter-Chip Link for High-Performance
and Low-Power 3D System Integration," Solid-State Circuits Technologies,
ISBN: 978-953-307-045-2, INTECH, pp. 281-306, Jan., 2010
< Domestic Conference Papers (国内会議発表論文) >
[1]若林和行、上森聡史、、山田貴文、小林修、加藤啓介、小林春夫、新津葵一、松浦達治、「ADCテスト信号生成のためのAWG非線形性補正技術」、第64回 FTC研究会、2011年1月
[2]湯本哲也、西村繁幸、村上健、土井祐太、三田大介、長谷川賀則、壇徹、内藤智洋、高橋伸夫、坂田浩司、小林春夫、高井伸和、新津葵一、「TVチューナ用広帯域ADPLLの高性能化技術」、第12回 DSPS教育者会議 2010年9月10日
[3] Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa,
Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, and Hideharu Amano, "MuCCRA-Cube:
a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link,"
情報処理学会 先進的計算基盤システムシンポジウム （SACSIS 2010） セッション4A-(12)、 2010年5月27日
[4]佐圓真、長田健一、大熊康介、新津葵一、島崎靖久、野々村到、杉森靖史、小浜由範、春日一貴、黒田忠広、「誘導結合を用いたプロセッサと複数メモリの三次元集積技術」、電子情報通信学会 VLSI設計技術研究会(VLD2010-5)、43-47頁、2010年5月20日
[5] 新津葵一、島崎 靖久、杉森 靖史、小浜 由範、春日 一貴、野々村 到、佐圓 真、小松 成亘、長田 健一、入江 直彦、服部 俊洋、長谷川 淳、黒田 忠広、「誘導結合通信を用いた低消費電力・高性能三次元プロセッサの開発 〜
90nm CMOSマルチコアプロセッサと65nm CMOS SRAMの三次元システム集積 〜」、電子情報通信学会 集積回路研究会(ICD2009-105)、163-168頁、浜松、2009年12月15日
[6] 新津葵一、島崎 靖久、杉森 靖史、小浜 由範、春日 一貴、野々村 到、佐圓 真、小松 成亘、長田 健一、入江 直彦、服部 俊洋、長谷川 淳、黒田 忠広、「誘導結合リンクを用いた90nmプロセッサと65nm
SRAMの三次元システム集積」、P-10、VDECデザイナーズフォーラム2009、東京、2009年6月
[7] 新津葵一、小浜由範、杉森靖史、長田健一、入江直彦、石黒仁揮、黒田忠広、「誘導結合リンクにおける積層チップ間位置合わせ誤差耐性のモデリングと実験的解析」、S-04、VDECデザイナーズフォーラム2009、東京、2009年6月
[8] 新津葵一、島崎靖久、杉森靖史、小浜由範、春日一貴、野々村到、佐圓真、小松成亘、長田健一、入江直彦、服部俊洋、長谷川淳、黒田忠広、「誘導結合リンクを用いた90nmプロセッサと65nm
SRAMの三次元システム集積」、LSIとシステムのワークショップ2009、福岡、2009年5月 (IEEE SSCS Japan Chapter
Academic Research Award を受賞)
[9] 新津葵一、川井秀介、三浦典之、石黒仁揮、黒田忠広、「低消費電力3次元システム集積に向けた65fJ/b誘導結合トランシーバ」、電子情報通信学会 集積回路研究会(ICD2008-114)、59頁、東京、2008年12月
[10] 新津葵一、「[招待講演]3次元システム集積のための低消費電力チップ間インタフェースの開発 ~A-SSCC2007発表報告を交えて~」 VDECデザイナーズフォーラム2008、大規模集積システム設計教育研究センター、東京、2008年6月
[11] 新津葵一、三浦典之、石黒仁揮、黒田忠広、「三次元システム集積のための積層チップ間誘導結合通信における低電力化に関する研究」、電子情報通信学会東京支部学生研究発表会、144頁、東京、2008年3月
[12] 黒田忠広、新津葵一、「[特別招待講演] 近接チップ間通信」、電子情報通信学会 集積回路研究会(ICD2006-176)、63-68頁、東京、2007年1月
[13] 井上眞梨、三浦典之、新津葵一、中川源洋、田子雅基、深石宗生、桜井貴康、黒田忠広、「誘導結合型チップ間無線通信における低消費電力デイジーチェーン送信器」、電子情報通信学会
集積回路研究会(ICD2006-90)、63-68頁、札幌、2006年8月
[14] 三浦典之、溝口大介、井上眞梨、新津葵一、中川源洋、田子雅基、深石宗生、桜井貴康、黒田忠広、「1Tb/s 3W チップ間誘導結合クロックデータトランシーバ」、電子情報通信学会 集積回路研究会(ICD2006-38)、95-100頁、神戸、2006年5月
[15] 新津葵一、三浦典之、溝口大介、黒田忠広、「誘導結合型チップ間無線超配線におけるクロストークの測定と解析」、電子情報通信学会 シリコンアナログRF研究会(RF2005-2)、8頁、東京、2005年8月
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